The disclosure relates in general to a memory controller. In particular, the disclosure relates to a memory controller for a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
Certain types of memory devices generate a clock strobe signal having edges aligned with changes in the read data. A DDR SDRAM transfers data on each rising and falling edge of the clock strobe signal, thereby transferring two data words per clock cycle.
A read, data synchronization circuit is often used to coordinate the transfer of data to and from a memory device, such as a DDR SDRAM. The read data synchronization circuit provides a local clock signal to the memory device to synchronize read and write operations. The clock strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by the read data synchronization circuit. The read data synchronization circuit uses the clock strobe signal to determine when the read data is valid and can therefore be latched. The times at which the read data is latched are preferably synchronized relative to the clock strobe signal so as to latch the read data in the middle of the valid data window.
Due to varying propagation delays from the read data synchronization circuit's local clock signal and the clock strobe signal received from the memory device, the phase relationship between the captured read data and the local clock signal from one device to the next and can change over time. These changes in phase alignment can be caused by input/output (I/O) pad delay variations, power supply fluctuations, process variations, temperature variations and variations in the clock input to data clock strobe output characteristics of the memory device. In certain cases these changes can be large enough to cause the captured read data to cross a metastable region with respect to the read data synchronization circuit's clock.
Due to these and other factors, accurate synchronization of captured read data to the read data synchronization circuit's clock requires the phase relationship between the data output clock strobe and the read data synchronization circuit clock to be maintained. Typically, a clock gating technique is employed which can introduce errors into data synchronization.
U.S. Pat. No. 6,603,706 to Nystuen provides a method and apparatus for synchronization of read data in a read data synchronization circuit, wherein programmable timing signals are provided for use in synchronizing read data.
However, the method and apparatus for synchronization of read data in a read data synchronization circuit provided by Nystuen requires a programmable logic to adjust latch points for reading data, and software or hardware programming the logic. In addition, since all bits on a bus may not be consentient, programmable logics are required for each bit of data accessing ports, increasing costs.